This invention relates to a clamp circuit, especially to a clamp circuit provided between a final amplifier stage and a cathode of a cathode ray tube (CRT), to process a video signal having a large amplitude and a wide range of frequency components.
One example of such a clamp circuit is disclosed in U.S. Pat. No. 4,285,008, issued to Osawa et al on Aug. 18, 1981. This clamp circuit has a capacitor connected between the final amplifier stage and the cathode of the CRT, an adjustable D.C. voltage source and switching means connected between the voltage source and the connecting point of the capacitor and the cathode. The switching means is turned on during the horizontal retrace period and off during the horizontal scan period of the video scanning.
Since the final video amplifier stage in the Osawa et al clamp circuit comprises two complementary transistors connected in an emitter follower configuration to form an SEPP amplifier, if the frequency of a video signal passing therethrough is lower than 10.about.20 MHz, the output impedance is so low that a full D.C. restoring operation is necessitated.
In general, the capacitor connected between the pre-amplifier stage and the output device is charged (or discharged) during a non-clamping period, which is the OFF period of the switching means, in accordance with the time constant determined by the output impedance of the pre-amplifier stage and the capacitance of the capacitor during the clamping period, which is the ON period of switching means. Therefore, a constant D.C. voltage is generated at the output side of the capacitor, if the electrical charge values of the charging and discharging are balanced. A decrease of the output impedance of the pre-amplifier stage causes a decrease of the time constant; therefore, it is necessary to perform the full D.C. restoring. However, this causes an increase of power consumption in the pre-amplifier stage. Thus, there is a dilemma produced by the output impendace of the pre-amplifier stage.